For ultra large scale integration (ULSI) semiconductor technologies nowadays, the dramatically increased of the integrated circuit density has downsizing the individual devices. Dynamic random access memory (DRAM) circuit is one of the integrated circuit types to experience the demand of increased density, which is used extensively in the electronics industry for information storage. Normally, one can evaluate the development of a semiconductor-manufacturing factory by the minimum conductive line, or the storage capacity of DRAM devices it can produce.
The memory cells of DRAM are comprised of two main components: a field-effect transistor (MOSFET) and a capacitor. A bit line and a word line is connected to source/drain area and gate area of MOSFET cell respectively. The other source/drain area of MOSFET is electrically connected to the capacitor. During operations, the digital signal of bit line is stored to the capacitor via the controlled voltage of word line. A single DRAM storage cell stores a bit of data on the capacitor as electrical charge. As component density in memory chips has increased, the shrinkage of cell capacitor size has resulted in a number of problems. Firstly, .alpha.-particle component of normal background radiation will generate hole-electron pairs in the n+silicon substrate plate of a cell capacitor. This phenomena will cause the charge within the affected cell capacitor to rapidly dissipate, resulting in a "soft" error. Secondly, the cell refresh time must be shortened due to the cell capacitance is reduced, thus more refresh interruptions are required.
Owing to all the problems described above, several stacked structures of capacitor are introduced to increase capacitance, such as fin shaped or crown shaped capacitor structure. Alternatively, another scheme involves the use of high dielectric constant materials such as Ta.sub.2 O.sub.5 or BaTiO.sub.3 to further increase the capacitance.
Although the efforts to provide adequate cell capacitance focus on creating complex three-dimensional capacitors and improving the dielectric materials, some problems are still exist in fabricating the DRAM cells. One of the problems is that the conventional lower capacitor node contact comprises semiconductor material such as doped polysilicon layer, which the interfacial reaction is inevitable. Besides, the capacitor node contact filling becomes increasingly difficult as a result of reduced device dimensions. For node contact with high aspect ratio (more than ten), it is not easy to use a Physical Vapor Deposition (PVD) method to fill barrier metal or use a Chemical Vapor Deposition (CVD) method to fill tungsten (W).
Although a considerable work has been done to improve the reliability of DRAM cells, there is still a strong need in the semiconductor industry to further improve the reliability of DRAM cells and to increase the capacitance of the stacked capacitors for DRAM cells. This is especially true when the semiconductor fabrication proceed to next decade.